(1) Field of the Invention
The present invention relates to a process for making local interconnections for DRAM circuits with low contact resistance. The process also reduces the number of masks by one, over the prior art, to provide a more cost-effective manufacturing process.
(2) Description of the Prior Art
Advances in high-resolution photolithography and anisotropic plasma etching have reduced the minimum feature sizes of semiconductor devices. For example, the current minimum feature size of the gate electrodes for field effect transistor (FET) semiconductor devices is sub-half-micrometer (um) (about 0.35 um or less). These discrete devices are electrically interconnected by multilevels of conducting layers with intervening insulating layers having contact openings. The reduced feature sizes require smaller contact openings for the electrically conducting interconnections that lead to higher contact resistance (R.sub.c). For example, current contact hole feature sizes are now typically much less than 0.5 micrometer (um), and to make contacts to the FET gate electrodes and for local interconnections, the contacts can be less than 0.35 um in width or diameter. The high R.sub.c is further complicated by the native oxide that forms between the conducting layers in the contact openings during processing. The increase in this parasitic contact resistance in series with circuit devices, such as FETs, degrades the circuit performance and therefore is undesirable. A further concern is the wide distribution in contact resistance (R.sub.c) that can occur over the large number of contact holes that are simultaneously etched, and is also very undesirable.
It is common practice in the semiconductor industry to interconnect the semiconductor devices by using multilayers of polycide formed from an electrical conductively doped polysilicon layer and a top silicide layer, and by patterned metal layers to complete the electrical connections on integrated circuits. Because of electrical device characteristics and temperature considerations, it is desirable to form the gate electrodes for FETs and the next level of electrical interconnections (local interconnections) from a patterned first and second level of polycide layers. An InterLevel Dielectric (ILD) layer, such as a silicon oxide (SiO.sub.2) is used between the patterned polycide layers to electrically insulate the various levels of patterned polycide layers. Contact holes are etched in the ILD layer to electrically interconnect the first and second polycide layers. On Ultra Large Scale Integration (ULSI), the number of contacts now well exceeds a million, and it is important to have consistently low and tight distributions of the contact resistance (R.sub.c).
This high contact resistance problem is of particular concern on DRAM chips between the two patterned tungsten polycide (silicide (WSi.sub.x)/polysilicon) layers used to form the FET gate electrodes and the local interconnections on the peripheral circuits of the DRAM chip, while concurrently forming the bit lines from the second polycide layer in the DRAM cell areas.
Unfortunately, when the contact holes are etched in the dielectric layer to the first polycide layer, and when the second polycide layer is deposited, it is difficult to achieve consistently low contact resistance. This high contact resistance results from the native oxide that rapidly forms on the WSi.sub.x of the first polycide layer in the contact openings prior to depositing the second polycide layer. For example, contacts having minimum feature sizes of 0.5 um or less can have contact resistance that exceeds 193 Kohms, which are essentially electrical opens.
One prior art method of reducing the contact resistance between the polycide layers in the peripheral circuits on a DRAM chip is depicted in FIGS. 1 and 2. As shown in FIG. 1, the sequence of process steps for making these low contact resistance interconnections involves providing a substrate 10, forming a field oxide (FOX) 12 to isolate the memory cell device areas as shown in portion A of FIG. 1, and for the peripheral circuit device areas as shown in portion B of FIG. 1. Next, a gate oxide 14 is formed on all the device areas. Then a doped first polysilicon layer 16 and a first silicide layer 18 are deposited and patterned to form a first polycide layer (16 and 18) for the FETs on the substrate 10 for the DRAM pass transistors, and word lines (portion A), while concurrently forming the FETs and parts of the local interconnections in the peripheral area (portion B). Lightly doped source/drain areas 17(N.sup.-) for the FETs are then formed by implanting a dopant, and a conformal insulating layer is deposited and anisotropically etched back to form insulating sidewall spacers 20 on the FET gate electrodes. Next, a second ion implantation is used to complete the source/drain contact areas 19(N.sup.+). An InterLevel Dielectric (ILD) layer 22 is deposited and planarized to insulate the underlying devices (FETs). Contact openings 2 are etched in the ILD layer 22 for the bit lines in the memory cell areas (portion A), and contact openings 3 and 4 are etched in the ILD layer to the substrate and to the first polycide layer, respectively, at the DRAM chip edge (portion B, FIG. 1) for the peripheral circuits. However, to minimize contact resistance, as shown in FIG. 1, the traditional approach is to use an additional photoresist mask (not shown) and an additional etching step to remove the first silicide layer 18 in the contact openings 4 to reduce the contact resistance that would otherwise result from the rapid oxidation of the WSi.sub.x prior to depositing the second polycide layer.
Now as shown in FIG. 2, the bit lines and the local interconnections are completed by depositing an electrically conducting doped second polysilicon layer 24 and a second WSi.sub.x layer 26 to form the second polycide layer. The second polycide layer (24 and 26) is then patterned to form the bit lines 5 in the memory cell area (portion A) and the local interconnections 6 and 7 in the peripheral device area (portion B).
Numerous methods have been reported for making integrated circuits with reduced contact resistance. In U.S. Pat. No. 5,744,395 by Shue et al. a method for making low resistance self-aligned titanium silicide structures for FET gate electrodes is described. A metastable phase of titanium silicide is deposited by CVD and a titanium layer is deposited and a rapid thermal anneal (RTA) is used to convert the silicide to a stable, low resistance silicide. In U.S. Pat. No. 5,759,882 to Kao et al., a method for making self-aligned contacts and local interconnections in CMOS circuits using Chemical Mechanical Polishing (CMP) is described. The method employs two RTA steps: a first RTA to activate the N.sup.+ dopant in the diffused devices, and a second RTA to form the conventional salicide process. Cheng et al., U.S. Pat. No. 5,728,615, teach a method of making polysilicon resistors with more uniform resistance. The method employs a thermal step to more uniformly distribute and equalize the hydrogen in the polysilicon resistor. U.S. Pat. No. 5,710,454 to Wu describes a method for making a tungsten silicide gate electrode using a stacked amorphous silicon (SAS) multilayer structure. The method incorporates conductive plugs, such as tungsten, to contact the FET source/drain and gate electrode. Also in U.S. Pat. No. 5,710,078 to Tseng, a method is described for making improved metal bit lines to underlying polycide structures. The method overetches the contact opening in the insulator to the underlying patterned silicide layer to expose the edges and thereby increase contact area and reduce the contact resistance. None of the above cited references addresses the problem of reducing the high contact resistance R.sub.c resulting from the unwanted native oxide at a polycide/polycide interface while concurrently making bit lines on a DRAM chip.
Therefore, there is still a need in the semiconductor industry to reduce the contact resistance between tungsten polycide layers, while reducing the number of processing steps on DRAM chips.